The present invention relates in general to interconnections within semiconductor circuits and methods of making the interconnections. More particularly, the present invention relates to interconnections which carry the greatest currents within the semiconductor circuits, referred to herein interchangeably as interconnects or large interconnects, and methods of making the interconnects to have low resistance and occupy reduced surface area. Since the large interconnects of the present application carry the greatest currents within the semiconductor circuits, they include, for example, power buses for conducting power within the semiconductor circuits.
A semiconductor circuit includes an array of devices which are interconnected by patterns of wiring lines formed of conductive material, some of the wiring lines connecting power to the devices. As the devices are scaled to smaller and smaller dimensions, formation of reliable interconnects becomes more and more difficult since the wiring lines need to be formed to occupy less chip space or surface area which is typically, at least in part, accomplished by reducing the width of the wiring lines. As the wiring lines are reduced in width, they eventually become so narrow that to reduce them further results in resistance levels which are too great for reliable operation of the semiconductor circuits. Resistance levels due to narrow wiring line widths is particularly problematic for power buses and other large interconnects which carry the highest currents within the semiconductor circuit.
To overcome the problems of further reduction of width for wiring lines, the depth of the lines has been increased. A method for increasing the depth of wiring lines is known as a damascene process which is named after the inlaid metal technique used in ancient Damascus to decorate swords and the like. In the damascene process, channels are etched into a generally planar insulation layer and a layer of conductive material is then formed over the insulation layer to fill the channels and form conductive ribs which are coupled to contact locations beneath the insulation layer. A planarization operation is then performed, for example by chemical mechanical planarization (CMP), to separate the inlaid ribs from one another.
Unfortunately, wiring lines used for large interconnects of a semiconductor circuit which are formed as ribs and produced, for example, by the damascene process, have height limitations such that the conductivity of the corresponding large interconnects is limited. Accordingly, this solution to the problem of providing ever smaller area wiring lines for interconnections is limited as well.
There is, thus, a need for improved interconnections for semiconductor circuits which will allow wiring lines to be formed within smaller surface areas yet provide lower resistances than can be produced by wiring lines formed as isolated conductive ribs.